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PRELIMINARY
W230
Spread Spectrum FTG for VIA K7 Chipset
Features
* Maximized EMI Suppression using Cypress's Spread Spectrum technology * Single chip system frequency synthesizer for VIA K7 chipset * Two copies of CPU output * Six copies of PCI output * One 48-MHz output for USB * One 24-MHz or 48-MHz output for SIO * Two buffered reference outputs * Thirteen SDRAM outputs provide support for 3 DIMMs * Supports frequencies up to 200 MHz * I2C interface for programming * Power management control inputs * Available in 48-pin SSOP Table 1. Mode Input Table Mode 0 1 Pin 2 CPU_STOP# REF0
Key Specifications
CPU Cycle-to-Cycle Jitter: .......................................... 250 ps CPU to CPU Output Skew: ......................................... 175 ps PCI to PCI Output Skew: ............................................ 500 ps VDDQ3: .................................................................... 3.3V5% SDRAMIN to SDRAM0:12 Delay: ..........................3.7 ns typ.
Table 2. Pin Selectable Frequency Input Address CPUT_CS CPUT0 PCI_F, Spread FS3 FS2 FS1 FS0 (MHz) 1:5 (MHz) Spectrum 1 1 1 1 100.0 33.3 -0.5% 1 1 1 0 100.0 33.3 0.25% 1 1 0 1 100.0 33.3 0.5% 1 1 0 0 95.0 31.7 OFF 1 0 1 1 133.3 33.3 -0.5% 1 0 1 0 133.3 33.3 0.25% 1 0 0 1 133.3 33.3 0.5% 1 0 0 0 102.0 34.0 OFF 0 1 1 1 104.0 34.6 OFF 0 1 1 0 106.0 35.3 OFF 0 1 0 1 107.0 35.6 OFF 0 1 0 0 108.0 36.0 OFF 0 0 1 1 109.0 36.3 OFF 0 0 1 0 110.0 36.6 OFF 0 0 0 1 111.0 37.0 OFF 0 0 0 0 112.0 37.3 OFF
Block Diagram
VDDQ3 REF0/(CPU_STOP#) X1 X2 XTAL OSC
PLL Ref Freq
Pin Configuration
REF1/FS0
[1]
I/O Pin Control
PWRDWN#
CPUT_CS Stop Clock Control
/2,3,4
PLL 1
CPUT0 CPUC0 VDDQ3 PCI0/MODE PCI1/FS1 PCI2 PCI3 PCI4 PCI5 VDDQ3 48MHz/FS2
SDATA SCLK
I2C Logic PLL2
/2
VDDQ3 REF0/(CPU_STOP#) GND X1 X2 VDDQ3 PCI0/MODE PCI1/FS1* GND PCI2 PCI3 PCI4 PCI5 VDDQ3 SDRAMIN GND SDRAM11 SDRAM10 VDDQ3 SDRAM9 SDRAM8 GND SDATA I2C SCLK
{
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
REF1/FS0* GND CPUT_CS GND CPUC0 CPUT0 VDDQ3 PWRDWN#* SDRAM12 GND SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDQ3 SDRAM6 SDRAM7 VDDQ3 48MHz/FS2* 24_48MHz/FS3^
SDRAMIN
13
24_48MHz/FS3 VDDQ3 SDRAM0:12
Note: 1. Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping. Unlike other I/O pins, input FS3 has an internal pull-down resistor.
W230
I2C is a trademark of Phillips Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 February 21, 2000, rev. **
PRELIMINARY
Pin Definitions
Pin Name CPUT0, CPUC0, CPUT_CS PCI2:5 Pin No. 43, 44, 46 Pin Type O (opendrain) O Pin Description
W230
CPU Clock Output 0: CPUT0 and CPUC0 are the differential CPU clock outputs for the K7 processor. CPUT_CS is the open-drain clock output for the chipset. It has the same phase relationship as CPUT0. PCI Clock Outputs 2 through 5: These four PCI clock outputs are controlled by the PWRDWN# control pin. Frequency is set by FS0:3 inputs or through serial input interface, see Tables 2 and 6 for details. Output voltage swing is controlled by voltage applied to VDDQ3. Fixed PCI Clock Output/Frequency Select 1: As an output, frequency is set by FS0:3 inputs or through serial input interface. This output is controlled by the PWRDWN# input. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 2. Fixed PCI Clock Output/Mode: As an output, frequency is set by the FS0:3 inputs or through serial input interface, see Tables 2 and 6. This output is controlled by the PWRDWN# input. This pin also serves as a power-on strap option to determine the function of pin 2, see Table 1 for details. PWRDWN# Input: LVTTL-compatible input that places the device in power-down mode when held LOW. In power-down mode,CPUC0 will be three-stated and all the other output clocks will be driven LOW. 48-MHz Output/Frequency Select 2: 48 MHz is provided in normal operation. In standard PC systems, this output can be used as the reference for the Universal Serial Bus host controller. This pin also serves as a power on strap option to determine device operating frequency as described in Table 2. 24_48-MHz Output/Frequency Select 3: In standard PC systems, this output can be used as the clock input for a Super I/O chip. The output frequency is controlled by Configuration Byte 3 bit[6]. The default output frequency is 48 MHz. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 2. Reference Clock Output 1/Frequency Select 2: 3.3V 14.318-MHz output clock. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 2. Upon power-up, FS0 input will be latched which will set clock frequencies as described in Table 2. Reference Clock Output 0 or CPU_STOP# Input Pin: Function is determined by the MODE pin. When CPU_STOP# input is asserted LOW, it will drive CPUT0 and CPUT_CS to logic 0, and it will three-state CPUC0. When this pin is configured as an output, this pin becomes a 3.3V 14.318-MHz output clock. Buffered Input Pin: The signal provided to this input pin is buffered to 13 outputs (SDRAM0:12). Buffered Outputs: These thirteen dedicated outputs provide copies of the signal provided at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when PWRDWN# input is set LOW. Clock pin for I2C circuitry. Data pin for I2C circuitry. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs, PCI outputs, reference outputs, 48-MHz output, and 24_48-MHz output. Connect to 3.3V supply Ground Connections: Connect all ground pins to the common system ground plane.
10, 11, 12, 13
PCI1/FS1
8
I/O
PCI0/MODE
7
I/O
PWRDWN#
41
I
48MHz/FS2
26
I/O
24_48MHz/ FS3
25
I/O
REF1/FS0
48
I/O
REF0/ CPU_STOP#
2
I/O
SDRAMIN SDRAM0:12
15 38, 37, 35, 34, 32, 31, 29, 28, 21, 20, 18, 17, 40 24 23 4
I O
SCLK SDATA X1
I I/O I
X2 VDDQ3
5 1, 6, 14, 19, 27, 30, 36, 42 3, 9, 16, 22, 33, 39, 45, 47
I P
GND
G
2
PRELIMINARY
Overview
The W230 was developed as a single-chip device to meet the clocking needs of VIA K7 core logic chip sets. In addition to the typical outputs provided by a standard FTG, the W230 adds a thirteenth output buffer, supporting SDRAM DIMM modules in conjunction with the chipset. Cypress's proprietary spread spectrum frequency synthesis technique is a feature of the CPU and PCI outputs. When enabled, this feature reduces the peak EMI measurements of not only the output signals and their harmonics, but also of any other clock signals that are properly synchronized to them.
W230
Upon W230 power-up, the first 2 ms of operation is used for input logic selection. During this period, the five I/O pins (7, 8, 25, 26, 48) are three-stated, allowing the output strapping resistor on the l/O pins to pull the pins and their associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic "0" or "1" condition of the l/O pin is latched. Next the output buffer is enabled converting the l/O pins into operating clock outputs. The 2-ms timer starts when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock outputs is <40 (nominal), which is minimally affected by the 10-k strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling. When the clock outputs are enabled following the 2-ms input period, the specified output frequency is delivered on the pin, assuming that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once VDD voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled.
VDD Output Strapping Resistor Series Termination Resistor R Clock Load
Functional Description
I/O Pin Operation Pins 7, 8, 25, 26, and 48 are dual-purpose l/O pins. Upon power-up these pins act as logic inputs, allowing the determination of assigned device functions. A short time after powerup, the logic state of each pin is latched and the pins become clock outputs. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-k "strapping" resistor is connected between the l/O pin and ground or VDD. Connection to ground sets a latch to "0," connection to VDD sets a latch to "1." Figure 1 and Figure 2 show two suggested methods for strapping resistor connections.
10 k (Load Option 1) W230 Output Buffer Power-on Reset Timer Output Three-state Hold Output Low
D
10 k (Load Option 0)
Q
Data Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options
VDD 10 k W230 Output Buffer Power-on Reset Timer Output Three-state Hold Output Low
D
Output Strapping Resistor Series Termination Resistor R Clock Load
Resistor Value R
Q
Data Latch
Figure 2. Input Logic Selection Through Jumper Option
3
PRELIMINARY
Spread Spectrum Frequency Timing Generator
The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 3. As shown in Figure 3, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is dB = 6.5 + 9*log10(P) + 9*log10(F)
W230
Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The output clock is modulated with a waveform depicted in Figure 4. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is specified in Table 6. Figure 4 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. Spread Spectrum clocking is activated or deactivated by selecting the appropriate values for bits 1-0 in data byte 0 of the I2C data stream. Refer to Table 6 for more details.
EMI Reduction SSFTG Typical Clo ck
Am plitu d e (d B )
Am plitude (d B)
Spread Spectrum Enabled
NonSpread Speactrum
Frequency Span (MHz) Center Spread
Frequency Span (MHz) Down Spread
Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX (0%)
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
MIN (-0.5%)
Figure 4. Typical Modulation Profile
4
100%
PRELIMINARY
Serial Data Interface
The W230 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the W230 initializes with default register settings, therefore the use of this serial data interface is optional. The serial interface is write-only (to the clock chip) and is the dedicated function of device pins SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic outputs of the Table 3. Serial Data Interface Control Functions Summary Control Function Clock Output Disable Description Common Application
W230
chipset. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 3 summarizes the control functions of the serial data interface. Operation Data is written to the W230 in eleven bytes of eight bits each. Bytes are written in the order shown in Table 4.
Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI abled outputs are actively held LOW. and system power. Examples are clock outputs to unused PCI slots. Provides CPU/PCI frequency selections through software. Frequency is changed in a smooth and controlled fashion. Enables or disables spread spectrum clocking. Puts clock output into a high impedance state. For alternate microprocessors and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. For EMI reduction. Production PCB testing.
CPU Clock Frequency Selection
Spread Spectrum Enabling Output Three-state (Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be writduction device testing. ten as 0.
Table 4. Byte Writing Sequence Byte Sequence 1 Byte Name Slave Address Bit Sequence 11010010 Byte Description Commands the W230 to accept the bits in Data Bytes 0-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W230 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the W230, therefore bit values are ignored ("don't care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the W230, therefore bit values are ignored ("don't care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. The data bits in Data Bytes 0-7 set internal W230 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 5, Data Byte Serial Configuration Map.
2
Command Code
Don't Care
3
Byte Count
Don't Care
4 5 6 7 8 9 10 11
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7
Refer to Table 5
5
PRELIMINARY
Writing Data Bytes Each bit in the data bytes controls a particular device function except for the "reserved" bits, which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit Table 5. Data Bytes 0-7 Serial Configuration Map Affected Pin Bit(s) 7 6 5 4 3 2 1 0 Data Byte 1 7 6 5 4 3 2 1 0 Data Byte 2 7 6 5 4 3 2 1 0 Data Byte 3 7 6 5 4 3 2 --26 25 -21, 20, 18, 17 -(Reserved) -24-MHz Low Low -Low -48-MHz Active Active -Active -7 -13 12 11 10 8 -PCI0 -PCI5 PCI4 PCI3 PCI2 PCI1 (Reserved) Clock Output Disable (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable -Low -Low Low Low Low Low -Active -Active Active Active Active Active ----40 -43, 44 46 ----SDRAM_12 -CPUT0, CPUC0 CPUT_CS (Reserved) (Reserved) (Reserved) (Reserved) Clock Output Disable (Reserved) Clock Output Disable Clock Output Disable ----Low -Low, Three-state Low ----Active -Active Active Pin No. --------Pin Name --------Control Function (Reserved) SEL_2 SEL_1 SEL_0 Hardware/Software Frequency Select SEL_4 SEL_3 Normal 0 -See Table 6 See Table 6 See Table 6 Hardware See Table 6 See Table 6 Three-stated Software Data Byte 0 -Bit Control 1
W230
7. Table 5 gives the bit formats for registers located in Data Bytes 0-7. Table 6 details additional frequency selections that are available through the serial data interface.
Default 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 0 1
SEL_48MHz SEL 48MHz as the output frequency for 24_48MHz 48MHz 24_48MHz -Clock Output Disable Clock Output Disable (Reserved)
SDRAM8:11 Clock Output Disable
6
PRELIMINARY
Table 5. Data Bytes 0-7 Serial Configuration Map (continued) Affected Pin Bit(s) 1 0 Pin No. 32, 31, 29, 28 38, 37, 35, 34 --------------48 2 ----------------Pin Name SDRAM4:7 SDRAM0:3 Control Function Clock Output Disable Clock Output Disable 0 Low Low Bit Control 1 Active Active
W230
Default 1 1
Data Byte 4 7 6 5 4 3 2 1 0 Data Byte 5 7 6 5 4 3 2 1 0 Data Byte 6 7 6 5 4 3 2 1 0 Data Byte 7 7 6 5 4 3 2 1 0 --------(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) ----------------0 0 0 0 0 0 0 0 --------(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) ----------------0 0 0 0 0 0 0 0 ------REF1 REF0 (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Clock Output Disable Clock Output Disable ------Low Low ------Active Active 0 0 0 1 0 0 1 1 --------(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) ----------------0 0 0 0 0 0 0 0
7
PRELIMINARY
Table 6. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions Data Byte 0, Bit 3 = 1 Bit 2 SEL_4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 1 SEL_3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Bit 6 SEL_2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 Bit 5 SEL_1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 Bit 4 SEL_0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CPU 100.0 100.0 100.0 95.0 133.3 133.3 133.3 102.0 104.0 106.0 107.0 108.0 109.0 110.0 111.0 112.0 113.0 114.0 115.0 116.0 118.0 120.0 124.0 127.0 130.0 136.0 140.0 145.0 150.0 155.0 160.0 166.0 PCI 33.3 33.3 33.3 31.7 33.3 33.3 33.3 34.0 34.6 35.3 35.6 36.0 36.3 36.6 37.0 37.3 37.6 38.0 38.3 38.6 39.3 40.0 31.0 31.7 32.5 34.0 35.0 36.2 37.5 38.7 40 41.6 Output Frequency
W230
Spread Spectrum -0.5% 0.25% 0.5% OFF -0.5% 0.25% 0.5% OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
8
PRELIMINARY
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions
.
W230
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 -55 to +125 0 to +70 2 (min.) Unit V C C C kV
Parameter VDD, VIN TSTG TB TA ESDPROT
Description Voltage on any pin with respect to GND Storage Temperature Ambient Temperature under Bias Operating Temperature Input ESD Protection
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5%
Parameter Supply Current IDD 3.3V Supply Current CPUT0, CPUC0, CPU_CS =100 MHz Outputs Loaded[2] CPUT0, CPUC0, CPU_CS =100 MHz Outputs Loaded[2] GND - 0.3 2.0 260 mA Description Test Condition Min. Typ. Max. Unit
IDD
2.5V Supply Current
25
mA
Logic Inputs VIL VIH IIL IIH VOL VOH VOL VOH IOL Input Low Voltage Input High Voltage Input Low Current[3] Input High Current[3] Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Current CPUT_CS, CPUT0, CPUC0 CPUT_CS, CPUT0, CPUC0 PCI0:5 REF0:1 48 MHz 24 MHz IOH Output High Current PCI0:5 REF0:1 48 MHz 24 MHz IOL = 1 mA IOH = -1 mA Termination to V pull-up (external) Termination to V pull-up (external) VOL = 1.5V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOH = 1.5V VOL = 1.5V VOL = 1.5V VOL = 1.5V 3.1 0 1.0 20.5 25 25 25 31 27 27 25 53 37 37 37 55 44 44 37 0.3 1.2 139 76 76 76 139 94 94 76 0.8 VDD + 0.3 -25 10 50 V V A A mV V V V mA mA mA mA mA mA mA mA
Clock Outputs
Notes: 2. All clock outputs loaded with 6" 60 transmission lines with 20-pF capacitors. 3. W230 logic inputs (except FS3) have internal pull-up devices (pull-ups not full CMOS level). Logic input FS3 has an internal pull-down device.
9
PRELIMINARY
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5%
Parameter Crystal Oscillator VTH CLOAD CIN,X1 CIN COUT LIN X1 Input Threshold Voltage[4] Load Capacitance, Imposed on External Crystal[5] X1 Input Capacitance[6] Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Pin X2 unconnected Except X1 and X2 VDDQ3 = 3.3V 1.65 14 28 5 6 7 Description Test Condition Min. Typ. Max.
W230
Unit V pF pF pF pF nH
Pin Capacitance/Inductance
AC Electrical Characteristics
TA = 0C to +70C, VDDQ3 = 3.3V5%, fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum is disabled. CPU Clock Outputs (CPUT0, CPUC0, CPUT_CS)[7] CPU = 100 MHz Parameter tR tF tD tJC tSK fST Description Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle to Cycle Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance Measured on rising edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. VO = VX 50 TBD 3 Measured at 50% point 45 Test Condition/Comments Min. Typ. Max. 1.0 1.0 55 250 TBD 3 45 CPU = 133 MHz Min. Typ. Max. 1.0 1.0 55 250 Unit V/ns V/ns % ps ps ms
Zo
50
Notes: 4. X1 input threshold voltage (typical) is VDD/2. 5. The W230 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 6. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). 7. Refer to Figure 5 for K7 operation clock driver test circuit.
10
PRELIMINARY
PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF Parameter tP tH tL tR tF tD tJC tSK tO fST Description Period High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew CPU to PCI Clock Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Measured on rising edge at 1.5V Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 30 1.5 Min. 30 12 12 1 1 45 4 4 55 250 500 4 Typ. Max.
W230
Unit ns ns ns V/ns V/ns % ps ps ns ms
Zo
REF0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF) Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 0.5 0.5 45 Min. Typ. 14.318 2 2 55 3 Max. Unit MHz V/ns V/ns % ms
Zo
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 48 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Determined by PLL divider ratio (see m/n below) (48.008 - 48)/48 (14.31818 MHz x 57/17 = 48.008 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 0.5 0.5 45 Min. Typ. 48.008 +167 57/17 2 2 55 3 V/ns V/ns % ms Max. Unit MHz ppm
Zo
11
PRELIMINARY
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 24 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Determined by PLL divider ratio (see m/n below) (24.004 - 24)/24 (14.31818 MHz x 57/34 = 24.004 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 0.5 0.5 45 Min. Typ. 24.004 +167 57/34 2 2 55 3 Max.
W230
Unit MHz ppm V/ns V/ns % ms
Zo
VDD + V1 3.3 Z0 = 52 ohms Length = 5" T1 R8 Z0 = 52 ohms Length = 3" T2
VDDCPU
VDDCPU + V2 1.5 R1 68
CPUCLK_T
47 20p
VDDCPU
Clock Chip CPU Driver
Z0 = 52 ohms Length = 5" T4 Z0 = 52 ohms Length = 3" T5
R3 68
CPUCLK_C
R9 47 29p
Figure 5. K7 Open Drain Clock Driver Test Circuit
Ordering Information
Ordering Code W230 Document #: 38-00890-** Package Name H Package Type 48-pin SSOP (300 mils)
12
PRELIMINARY
Layout Diagram
+3.3V Supply FB
VDDQ3
W230
C4
0.005 F
10 F
C3
F
G
G V 1 VCore G 2 3G 4 5G 6V 7G 8 9G 10 11 12 13 G 14 V 15 G 16 17 18 G 19 V 20 G 21 22 G 23 24 G
G
DDQ3
G
G
G
48 47 46 G 45 44 G 43 V 42 G 41 40 G 39 38 37 V 36 G 35 34 G 33 32 31 V 30 G 29 28 27 26 G 25
G
G C1
C2
G
FB = Dale ILB1206 - 300 (300 @ 100 MHz) C1 & C3 = 10-22 F C2 & C4 = 0.005 F C5 = 47 F C6 = 0.1 F
G = VIA to GND plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors
W 230
13
G
G
VDDQ3
5
C5 G
G C6
V =VIA to respective supply plane layer
PRELIMINARY
Package Diagram
48-Pin Small Shrink Outline Package (SSOP, 300 mils)
W230
Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102
(c) Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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